1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to texture buffer and controller architecture.
2. Description of the Related Art
With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data and data rates places additional burden on the memory systems that form an integral part of the graphics system. Attempts to further improve graphics system performance are now running up against the limitations of these memory systems in general, and memory device limitations in particular.
One example of a memory sub-system defining the upper limit of overall system performance may be the texture buffer of a graphics system. Certain graphics applications such as 3D modeling, virtual reality viewers, and video games may call for the application of an image to a geometric primitive in lieu of a procedurally generated pattern, gradient or solid color. In these applications, geometric primitives carry additional mapping data (e.g., a UV, or UVQ map) which describes how the non-procedural data is to be applied to the primitive. To implement this type of function, a graphics system may employ a texture buffer to store two dimensional image data representative of texture patterns, xe2x80x9cenvironmentxe2x80x9d maps, xe2x80x9cbumpxe2x80x9d maps, and other types of non-procedural data.
During the rendering process, the mapping data associated with a primitive may be used to interpolate texture map addresses for each pixel in the primitive. The texture map addresses may then be used to retrieve the portion of non-procedural image data in the texture buffer to be applied to the primitive. In some cases (e.g., photo-realistic rendering) a fetch from the texture buffer may result in a neighborhood or tile of texture pixels or texels to be retrieved from the texture buffer and spatially filtered to produce a single texel. In these cases, four or more texels may be retrieved for each displayed pixel, placing a high level of demand on the texture buffer. Thus, poor performance of the texture buffer is capable of affecting a cascading degradation through the graphics system, stalling the render pipeline, and increasing the render or refresh times of displayed images.
In some cases, dynamic random access memory (DRAM) devices may be used to implement a texture buffer as they are generally less expensive and occupy less real estate than static random access memory (SRAM) alternatives. However, DRAM devices have inherent factors such as pre-charge times, activation times, refresh periods, and others which may complicate integration into high bandwidth applications (e.g., high performance graphics systems). Recent advances in DRAM technology, including the introduction of new families (e.g., SDRAM) have increased the throughput of DRAM memories, but have not overcome all of these performance hurdles. Economically, the use of DRAM devices in graphics systems is still desirable, and possible if the above mentioned performance limiting factors can be mitigated through consideration of certain features unique to graphics systems (e.g., memory bandwidth has a higher priority than memory latency). For these reasons, a system and method for optimizing the utilization of DRAM memory sub-systems as employed in graphics systems is desired.
The problems set forth above may at least in part be solved in some embodiments by a system or method for optimizing a DRAM memory system through the employment of a request queue and memory status registers. In one embodiment, the system may include an interleaved memory of DRAM devices configured to receive, store, and recall image data. A request queue may be configured to receive and store pending requests for data from the memory, and a set of status registers may be configured to indicate the state of each interleave in the memory. A memory controller may be connected to the request queue, the status registers, and the memory. The memory controller may be configured to search the request queue for pending requests for data from each of the interleaves, and query the status registers to determine whether the interleaves are ready to be accessed. If there is a pending request targeted for an interleave which is not ready for access, the memory controller may assign urgent priority to precharging and activating that interleave. The memory controller may also remove requests from the request queue and issue them to interleaves that are ready for access, independent of the precharging and activation of non-ready interleaves.
As noted above, a method for optimizing a DRAM memory system through the employment of a request queue and memory status register is also contemplated. In one embodiment, the method includes maintaining a list of pending requests for data from the memory, and maintaining a status report for each interleave of the memory. The information in the status report may describe a given interleave as precharging, precharged, or active. The list of pending requests may be scanned for requests for data from each interleave in the memory. For each interleave, the request least recently added to the request queue may be chosen, and the interleave page address extracted from the request. Next, the associated status report may be examined to determine the state of the interleave. If the status report indicates that the interleave is active with the wrong row, then a command may be issued to begin a precharge cycle on the interleave. If the status report indicates that the interleave is precharged, then a command may be issued to activate the interleave, thus making the page address of the request the active page. If the status report indicates that the interleave is precharging, then no command may be issued. The request that was least recently sent to the request queue may then be removed from the request queue and issued to the associated interleave if the interleave is currently in an active state.